A focal plane array includes a two-dimensional array of detector elements, or pixels, organized by columns and rows. FIG. 1 is a block diagram one of example of an array 195 of pixels 190. It is common for a circuit within the pixel 190 to be able to accumulate charge from a photo-diode 105, corresponding to the flux 110 of light of various wavelengths. Often, the charge is accumulated on a capacitive element 115 which effectively integrates charge, producing a voltage, the voltage corresponding to the intensity of the flux 110 over a given time interval called an integration interval. In the example illustrated in FIG. 1, the photo-diode 105 is coupled to the capacitive element 115 via a MOS transistor or direct injection gate 120 that is biased with a voltage Vbias. In FIG. 1, circuit element 135 comprises circuitry capable of resetting the voltage of capacitive element 115 back to an initial condition and circuitry capable of conveying a charge or voltage to a column (or row) wire 180 for transfer to an output of array 195. Such a voltage or charge can be digitized by circuitry associated with the focal plane array resulting in binary values, at least one value for each pixel 190 of the focal plane array 195. Thus, a focal plane array can be used to convert a two-dimensional pattern of flux into a two-dimensional array of binary values, such resulting array often called a digital image.
The effective amount of charge that is accumulated by a pixel 190 over an integration interval can be increased by the addition of a digital counter circuit. In some examples, each pixel is given a unique digital counter circuit. Additional circuitry can be added to the pixel to allow a predetermined amount of charge to be removed from the capacitive element of the pixel and correspondingly increase the value of the digital counter by one count. Thus, over the lapsed period of time of an integration interval, the capacitive element 115 of the pixel 190 can integrate photo charge, a circuit within the pixel can remove predetermined quantities of charge, and a digital counter can count the number of charge removals. In this manner, the effective amount of charge that is accumulated by the pixel over an integration interval can be increased because the digital counter extends the integration range of the capacitive element.
The type of digital counter used to record charge removals can be of any logical variation, including binary, gray code, Linear-Feedback-Shift-Register (LFSR), or any other digital count circuit that can count charge removals. Furthermore, the relative sign of the charge removal can be plus or minus, relative to circuit ground, so a charge removal could be viewed as a charge addition in some cases.
A class of pixel circuits called “digital pixels” or “in-pixel ADCs” feature a digital counter circuit within each pixel, as illustrated in FIG. 2. A common digital pixel circuit features a capacitive element 115 for integrating photo charge to produce a voltage, a comparator 125 which detects when the voltage exceeds a reference voltage, a charge removal circuit 135 which removes a predetermined fixed amount of charge from the capacitive element 115, and a digital counter circuit 145 which increments each time an amount of charge is removed from the capacitive element. Reset logic 140 supplies a clock-type signal to the charge removal circuit 135, triggering the charge removal circuit to remove the predetermined amount of charge from the capacitive element 115 responsive to a signal from the comparator 125 indicating that the voltage across the capacitive elements has exceeded the reference voltage. With each charge removal/reset event, the digital counter 145 is incremented. The value of the digital counter 145 may be read out via a tri-state gate 150 on a data-out line 180, as shown in FIG. 2. Multiple other means of conveying the value of digital counter 145 to a set of outputs exist as alternatives to tri-state gate 150, as will be appreciated by those skilled in the art. For example, the values may be shifted out.
In a common digital pixel circuit, the size of the capacitive element is often reduced to a relatively small value (for example, 1.0 femto-farads or 10 femto-farads) and the number of counter bits is some number of bits that results in a large range of count values, for example 16 bits. Correspondingly, the voltage range of the capacitive element 115 is often relatively small, for example 250 millivolts. In this configuration, the digital counter 145 can act as an analog-to-digital converter, resulting in the ability of the circuit of a pixel to perform analog-to-digital conversion and thus be referred to as an “in-pixel ADC” circuit. The predetermined amount of charge can also be called a “quanta” of charge. The charge removal from the capacitive element 115 may be a reset back to a first voltage using a simple device such as a MOSFET. The charge removal may also be a more complex circuit that removes a quantum of charge causing the capacitive element voltage to go from one value to a second value.
There are several negative attributes of the above-discussed conventional digital pixels. In particular, the digital counter circuit 145 consumes finite area within each pixel 190. If the fabrication process of the circuit is relatively low density (for example 180 nanometers CMOS), the digital counter area might occupy nearly all of the available area within the pixel leaving negligible area for the capacitive element 115, the comparator 125, and the charge removal circuit 135. As discussed above, the pixel 190 may also include biasing circuits such as a direct injection gate MOSFET 120, for example, and negligible area might be available for that device or devices also. In these cases, where negligible or insufficient room for these or other circuit devices exist within the pixel area, the performance of these circuits may be degraded. Thus, noise, for example, may be increased substantially. In addition to digital counter circuits 145 restricting available area and thus limiting the quality of the analog circuits (such as the capacitive element 115, the comparator 125, and the charge removal circuit 135), the restricted area also limits capacity of the digital pixel. More specifically, the size of the capacitive element 115 may be restricted to less total charge storage, and which may limit the overall input flux capability of the pixel 190, possibly to less than what is needed for a given end application.
Conversely, if the fabrication process of the circuit is relatively high density (for example, 65 nanometers CMOS), there may be adequate room for the capacitive element 115, the comparator 125, the charge removal circuit 135, and bias circuitry 120; however, the associated non-recurring design cost of these processes may be too high for some consumers of such devices.
Another negative attribute is that when a digital counter circuit 145 resides with analog circuits, such as the capacitive element 115, comparator 125, charge removal circuit 135, and biasing devices 120, the instantaneous currents associated with digital counter switching events may create noise voltages in the supply lines and in the CMOS substrate potential, leading to increased noise and decreased quality performance of the analog circuits.
In some cases, the comparator circuit 125 sends a clock signal to the digital counter circuit 145 instantaneously when the voltage on the capacitive element 115 reaches the threshold of the comparator circuit. This same clock signal also causes the charge removal circuit 135 to remove a quantum of charge from the capacitive element. Such circuits are referred to as “asynchronous” digital pixels because there is no outside timing strobe used or required for the counting operation. Asynchronous digital pixel circuits are desirable because they are compact, relatively simple, and can be of lower power than a similar circuit that requires a timing strobe. However, it is also the case that asynchronous digital pixels can create instantaneous power supply perturbations of unpredictable timing leading to random power supply transient voltages and random substrate voltage fluctuations, further increasing noise and decreasing quality of the analog circuits. Furthermore, when the total incident flux 110 on the focal plane array is relatively high, the aggregation of the unpredictable supply transients created by an array of digital pixels can substantially degrade the quality of the analog circuits.
A further negative attribute of having digital counters in digital pixels is that the supply metal lines to the digital counters 145 consumes a percentage of available total routing of metal lines to each pixel 190. Similarly, the output bits of the counters require routing to the edges of the focal plane array 195, further consuming available routing area. The combination of supply wires and output bit routing wires consumes area that is often needed to increase the number and width of wires to the analog circuits of the pixels which could, if the area were available, reduce the resistance of the analog supply wires, thereby leading to improved analog performance. Along with this factor, further pixel area is consumed with output-capable circuits that are added to allow the counter values to be read out to the edges of the focal plane array 195. Such circuits may include tri-state drivers 150, dynamic pull-down multiplexors, shift registers, or any other circuits that are configured to propagate the digital counter values out to the edges of the focal plane array 195.
Referring to FIG. 3, another negative attribute is that if “integrate-while-read” capability is required, then an additional set of digital storage elements (for example, latches 155) also have to be installed within the pixel 190, further exacerbating the problems associated with having digital counters 145 in digital pixels, as described above. In integrate-while-read mode, at the end of an integration interval, the value of the digital counter 145 is copied to the digital storage element 155, preserving the values for read-out, for example, one row or one column at a time, and freeing up the digital counter 145 to be used for further counting of integrated charge.
Thus, a digital pixel circuit includes a digital counter circuit which can increase the overall charge storage capacity of a pixel. Simultaneously, though, the digital pixel circuit has several negative attributes which may limit its uses.